#riscv

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools

ncnn is a high-performance neural network inference framework optimized for the mobile platform

Modern, secure, portable, multiprotocol bootloader and boot manager.

Synth — WebAssembly-to-native compiler for ARM Cortex-M/R (Thumb-2/A32), RISC-V RV32, and AArch64, with mechanized Rocq correctness proofs, per-compilation translation validation, and sound WCET bounds. Part of the PulseEngine toolchain.