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#systemverilog

Every repository in the public record carrying this tag — from its GitHub topics or the keywords its package registries publish. Health is measured under the same versioned methodology as the rest of the record.

6 records
Tagged “systemverilog”Ranked by health index
PyPI
92Excellenthealth index
MikePopoloski/slang
SystemVerilog compiler and language services
C++★ 1,141Sep 17, 2026
MITSep 17, 2026 · metrics 2.10.0
crates.io
89Excellenthealth index
veryl-lang/veryl
Veryl: A Modern Hardware Description Language
Rust★ 1,046↓ 25.3K/moOct 18, 2026
Apache-2.0Oct 18, 2026 · metrics 2.10.0
PyPI · npm
77Goodhealth index
rtl-buddy/rtl_buddy
RTL Buddy is a Python CLI for Verilog and SystemVerilog regression testing, Verilator and VCS simulation workflows, coverage, and YAML-based RTL verification automation.
Python★ 3↓ 3,699/moSep 18, 2026
BSD-3-ClauseSep 18, 2026 · metrics 2.10.0
PyPI · npm · crates.io +1
60Moderatehealth index
gmlarumbe/tree-sitter-systemverilog
SystemVerilog tree-sitter grammar
JavaScript★ 58↓ 73.2K/moSep 10, 2026
MITSep 10, 2026 · metrics 2.10.0
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24At Riskhealth index
davemuscle/sigma_delta_converters
Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
SystemVerilog · Verilog · Python★ 87Sep 16, 2026
No licenseSep 16, 2026 · metrics 2.10.0