All tags
Catalogue tag

#verilog

Every repository in the public record carrying this tag — from its GitHub topics or the keywords its package registries publish. Health is measured under the same versioned methodology as the rest of the record.

7 records
Tagged “verilog”Ranked by health index
PyPI
96Exceptionalhealth index
cocotb/cocotb
cocotb: Python-based chip (RTL) verification
Python · C · C++★ 2,471Aug 13, 2026
BSD-3-ClauseAug 13, 2026 · metrics 2.10.0
PyPI
94Exceptionalhealth index
FPGA-Research/FABulous
An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
Python★ 279↓ 339/moJul 21, 2026
Apache-2.0Jul 21, 2026 · metrics 2.10.0
PyPI
93Exceptionalhealth index
siliconcompiler/siliconcompiler
Modular hardware build system
Python★ 1,187Jul 20, 2026
Apache-2.0Jul 20, 2026 · metrics 2.10.0
PyPI
92Excellenthealth index
MikePopoloski/slang
SystemVerilog compiler and language services
C++★ 1,110Aug 13, 2026
MITAug 13, 2026 · metrics 2.10.0
PyPI
77Goodhealth index
rtl-buddy/rtl_buddy
RTL Buddy is a Python CLI for Verilog and SystemVerilog regression testing, Verilator and VCS simulation workflows, coverage, and YAML-based RTL verification automation.
Python★ 3↓ 3,758/moAug 15, 2026
BSD-3-ClauseAug 15, 2026 · metrics 2.10.0
PyPI
75Goodhealth index
najaeda/naja
Netlist API (and more) for EDA flow development
Verilog · C++★ 149↓ 16.9K/moJul 22, 2026
Apache-2.0Jul 22, 2026 · metrics 2.10.0